The present invention relates to a semiconductor memory apparatus. More particularly, the present invention relates to an input circuit of a semiconductor memory apparatus, and a control method thereof.
A conventional semiconductor memory apparatus, for example, a 512M memory, is controlled using a chip selection signal and an address signal.
Meanwhile, additional control signals are necessary to control a 1 G memory as compared with the 512M memory.
The chip selection signal and the address can be used as the additional control signals by increasing the number of the chip selection signal and the address signal.
In the case of a control scheme of increasing the number of the chip selection signals, since the 1 G memory can be used as two 512M memories, a memory control speed can be increased. In the case of a control scheme of increasing the number of the address signals, integration capacity can be increased as compared with the control scheme of increasing the number of the chip selection signals.
An input circuit of a semiconductor memory apparatus according to the prior art includes pins for receiving the increased chip selection signal and address signal, or pins for receiving only one of the increased chip selection signal and address signal according to the control scheme.
The input circuit for receiving the increased chip selection signal or address signal processes only one signal according to the control scheme regardless of the configuration of the pins.
Thus, various configurations of the pins, which receive the increased chip selection signal and the increased address signal, and a control scheme, which can reduce limitation factors of a semiconductor memory apparatus, are required.